Fully-functioning Microprocessor
A VHDL microprocessor combining D latches, a Moore FSM, a 4:16 decoder, and three interchangeable ALU cores - each built to a different assigned instruction set - simulated and waveform-verified in Quartus.
Why it exists
The final project in a digital logic course, meant to fold every earlier assignment's building block into one working circuit - latches, a finite state machine, a decoder, and an ALU - all driven by a single clock and implemented on an FPGA board.
Four components, one clock
Two independent paths meet at the ALU: the data path just holds the operands, while the control path decides what to do with them.
Data path
A, B
Latch1 / Latch2
gated D, active-low reset
Control path
data_in
FSM (Moore)
9 states, s0 - s8
4:16 decoder
one-hot, 16-bit op call
ALU core
Result[7:0], Neg
The actual Quartus schematic - both latches and the control unit feeding the ALU core.
A state machine with a signature
The FSM cycles s0 through s8 one step at a time on each data_in pulse, wrapping back to s0 after. Every state does two things at once: it outputs one fixed digit of a personal 9-digit sequence baked directly into the VHDL (a small way of signing the circuit), and it passes its own 4-bit state value to the decoder, which turns it into a 16-bit one-hot code - exactly one bit set, uniquely identifying which of the ALU's nine functions to run next.
The actual Moore state diagram - nine states, each with its own fixed output digit.
Three ALUs, three assignments
Same latches, same FSM, same decoder, same 16-bit op-call convention - the only thing that changes between problems is what each of the nine codes actually means:
ALU_1
The default instruction set
- sum(A, B)
- diff(A, B)
- NOT A
- NAND(A, B)
- NOR(A, B)
- AND(A, B)
- XOR(A, B)
- OR(A, B)
- XNOR(A, B)
ALU_2
A personally assigned instruction set
- splice odd bits of A with odd bits of B
- NAND(A, B)
- sum(A, B) - 5
- 2's complement of B
- invert the even bits of B
- shift A left 2 bits (new bits = 0)
- always output 0
- 2's complement of A
- rotate B right 2 bits
ALU_3
Not arithmetic at all - a comparator
- compare each hex digit of A against the FSM's current output digit
- Y = 1 if either digit of A is larger, else Y = 0
What actually broke
Three real bugs from the build, straight from the report's own troubleshooting notes:
Inverted reset polarity
The latches were written to clear on Resetn = '0', but the reference waveform used to check against reset with a '1' - every comparison against it looked like a failure until the actual mismatch was spotted.
Quartus project corruption
Splitting waveforms across multiple simulation files inside one project (against the manual's advice) quietly corrupted files, so new inputs kept replaying old outputs - fixed only by starting a clean project.
A silently-zeroed variable
ALU_2's "sum(A, B) - 5" function first summed into a new intermediate signal, then subtracted 5 from it - but Quartus reset that signal to 0 first, turning the result into -5. Assigning straight into the existing result signal instead of a fresh one fixed it.
Solo work in VHDL, synthesized and simulated in Quartus. Each component was verified against its own waveform before being wired into the next - latches, then the FSM, then the decoder, then each ALU - so every failure could be traced to exactly one piece rather than the whole circuit at once.